1. Field of the Invention
The invention relates to a solid-state imaging element and a method for producing a solid-state imaging element. More particularly, the invention relates to a solid-state imaging element having a high-melting metal silicide formed in a CMOS circuit region without a high-melting metal silicide formed in a pixel region, and a method for producing the same.
2. Description of the Related Art
A CMOS solid-state imaging element has a pixel region generating charges by light irradiation (photodiode) and a transistor to read the charges generated in the light receiving region as signals (MOS transistor), both formed on a common substrate.
A non-silicided transistor is used as a CMOS transistor in a pixel, and a silicided transistor is used as a MOS transistor in a peripheral circuit.
The silicided MOS transistor has a high-melting metal silicide layer formed on a surface of a polysilicon gate electrode and a surface of a source/drain region.
The non-silicided MOS transistor has a salicide block film formed by a silicon nitride film to prevent silicidation of the transistor.
Since a source/drain injection step is carried out after the salicide block film formation step, the source/drain injection step for the silicided transistor differs from that for the non-silicided transistor (see Japanese Unexamined Patent Application Publication No. 2004-127957 and Japanese Unexamined Patent Application Publication No. 2005-174968, for example).
A method for producing a CMOS solid-state imaging element of the related art will be described with reference to FIGS. 1 to 3.
In FIGS. 1 to 3, only one gate electrode among a plurality of electrodes in a transistor formed in a pixel region and one gate electrode among a plurality of electrodes in a transistor formed in a logic circuit region are described as examples with reference to cross-sectional views, respectively.
First, a gate electrode 61 of a pixel transistor Tr is formed by a polysilicon film on a pixel region 60 of a semiconductor layer 200 through a gate insulating film 62. Then, a gate electrode 71 of a circuit transistor Tr is formed by a polysilicon film on a logic circuit region 70 through a gate insulating film 72.
Then, as shown in FIG. 1A, n-type impurities, for example, phosphorus (P) ions are injected into the semiconductor layer 200 using the gate electrodes 61 and 71 as masks to form n− regions 65 and 75 having an LDD structure in the semiconductor layer 200.
Next, an HTO (High Temperature Oxide) film 50 is formed by silicon oxide in each of the logic circuit region 70 and the pixel region 60, and a salicide block film as a SiN film (LP-SiN film) 51 formed by low pressure CVD is further deposited on the HTO film 50 as a silicon nitride film. Then, as shown in FIG. 1B, the LP-SiN film 51 in the pixel region 60 is covered with a photoresist 63.
Next, after covering the LP-SiN film 51 in the pixel region 60 with the photoresist 63, the salicide block film in the logic circuit region 70 is etched back. Accordingly, as shown in FIG. 1C, a sidewall 52 is formed by the HTO film 50 and the LP-SiN film 51 on a side surface of the gate electrode 71.
Next, as shown in FIG. 2D, the photoresist 63 is removed, and then a whole surface of each of the pixel region 60 and the logic circuit region 70 is covered with an HTO film 53. Then, the HTO film 53 is etched back.
Accordingly, as shown in FIG. 2E, a salicide block film 54 is formed by three layers of the HTO film 50, the LP-SiN film 51, and the HTO film 53 on the side surface of the gate electrode 71 of the logic circuit region 70.
In the pixel region 60, a salicide block film 55 is formed by the HTO film 50, the LP-SiN film 51, and the HTO film 53 with the HTO film 50 and the LP-SiN film 51 remaining on the whole surface of the pixel region 60.
Then, as shown in FIG. 2F, the pixel region 60 is covered with a photoresist 64, and then n-type impurities, for example, phosphorus (P) ions are injected using the salicide block film 54 in the logic circuit region 70 as a mask to form an n-type high impurity concentration region (n+ region) 76 in the semiconductor layer 200.
Here, n-type impurities are not injected into the pixel region 60 due to the presence of the photoresist 64.
The photoresist 64 is removed after this step.
Next, as shown in FIG. 3G, the logic circuit region 70 is covered with a photoresist 73, and then n-type impurities, for example, phosphorus (P) ions are injected using the HTO film 53 in the pixel region 60 as a mask to form an n-type high impurity concentration region (n+ region) 66 in the semiconductor layer 200. In ion injection shown in FIG. 3G, n-type impurities are injected into the pixel region 60 through the HTO film 50 and the LP-SiN film 51. Therefore, it may be necessary to make implantation energy for ion injection into the pixel region 60 higher than implantation energy in forming the n+ region 76 in the logic circuit region 70.
Here, n-type impurities are not injected into the logic circuit region 70 due to the presence of the photoresist 73.
Next, as shown in FIG. 3H, the photoresist 73 is removed, and then a high-melting metal film 56 is formed on the whole surface of each of the pixel region 60 and the logic circuit region 70.
Next, silicon is reacted with the high-melting metal to form high-melting metal silicide layers 77 and 78 on a surface of the gate electrode 71 and a surface of the n+ region 76 in the logic circuit region 70, respectively.
Next, as shown in FIG. 3I, an excess of the high-melting metal film 56 is removed to form the non-silicided pixel region 60 and the silicided logic circuit region 70.